Patent AT-E400853-T1: [Translated] METHOD AND APPARATUS FOR FORMAL CIRCUIT VERIFICATION
A method and apparatus for determining the time behavior of a digital circuit based on a starting assumption is disclosed. Generally, in a formal verification of a digital circuit, the time behavior of a digital circuit is monitored to verify or refute whether formulated properties, which comprise an assumption and an assertion, result as a consequence of a presence of an assumption in the digital circuit. In order to determine the behavior of the digital circuit, the time behavior of the digital circuit is examined from a starting initial state of the digital circuit. A relevant auxiliary property is activated and the assertion of the auxiliary property is added to the digital circuit. The digital circuit is then monitored over a period of time.
Complete Metadata
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| description | A method and apparatus for determining the time behavior of a digital circuit based on a starting assumption is disclosed. Generally, in a formal verification of a digital circuit, the time behavior of a digital circuit is monitored to verify or refute whether formulated properties, which comprise an assumption and an assertion, result as a consequence of a presence of an assumption in the digital circuit. In order to determine the behavior of the digital circuit, the time behavior of the digital circuit is examined from a starting initial state of the digital circuit. A relevant auxiliary property is activated and the assertion of the auxiliary property is added to the digital circuit. The digital circuit is then monitored over a period of time. |
| distribution |
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| identifier | https://healthdata.gov/api/views/br5s-4fu3 |
| issued | 2025-09-05 |
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| modified | 2025-09-06 |
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| title | Patent AT-E400853-T1: [Translated] METHOD AND APPARATUS FOR FORMAL CIRCUIT VERIFICATION |
