Patent AT-E400892-T1: [Translated] PRODUCTION PROCESS FOR CMOS SEMICONDUCTOR COMPONENTS WITH SELECTABLE GATE THICKNESS
The present invention discloses a method for obtaining layers, manufactured in the same device material, with different thickness or layer height. A specific example of such a process is a CMOS process comprising nMOS and pMOS devices with different gate electrode thickness. After forming the device material layer or gate electrode layer (2) disposable parts (4) are formed in selected regions (3) of this device layer (2). Preferably disposable parts are formed by doping the selected regions (3) to the required depth d. The as-deposited thickness t of this device (2) layer will be adjusted or modulated after the patterning of the individual devices by removing the disposable parts (4).
Complete Metadata
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| description | The present invention discloses a method for obtaining layers, manufactured in the same device material, with different thickness or layer height. A specific example of such a process is a CMOS process comprising nMOS and pMOS devices with different gate electrode thickness. After forming the device material layer or gate electrode layer (2) disposable parts (4) are formed in selected regions (3) of this device layer (2). Preferably disposable parts are formed by doping the selected regions (3) to the required depth d. The as-deposited thickness t of this device (2) layer will be adjusted or modulated after the patterning of the individual devices by removing the disposable parts (4). <IMAGE> |
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| issued | 2025-09-05 |
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| title | Patent AT-E400892-T1: [Translated] PRODUCTION PROCESS FOR CMOS SEMICONDUCTOR COMPONENTS WITH SELECTABLE GATE THICKNESS |
