Patent AT-E400924-T1: [Translated] METHOD FOR DYNAMIC SYMMETIZATION OF SERIES AND PARALLEL-CONNECTED POWER SEMICONDUCTOR SWITCHES
A method for dynamically balancing the loads in a circuit ( 1, 4 ) of semiconductor power switches arranged in series or in parallel is disclosed. Individual switching signals (iG1, iG2) for the semiconductor power switches (S1 . . . S4) are generated by determining a system-widely valid synchronous sampling time (tsj) independently for each semiconductor power switch (S1 . . . S4) due to a synchronous event (es) of the whole circuit ( 1, 4 ). Control loop offsets between actual values (ai) measured synchronously at the sampling time (tsj) and given desired values (as) of an asynchronous state variable (a(t)) of the semiconductor power switches (S1 . . . S4) are reduced in the same or in following switching cycles. Alternatively, control loop offsets between actual time values (tai) and desired time values (tas) are minimized, wherein the actual time values (tai) are measured upon exceeding a globally provided threshold value (epsilona) of an asynchronous state variable (a(t)) of the semiconductor power switches (S1 . . . S4). Embodiments relate to: Offsetting the sampling time (tsj) in time by a globally provided time interval (Deltat 0 ), providing desired values locally or globally, e.g. by averaging of actual values (ai, tai), additional balancing of the gradients of asynchronous time variables (a(t)). A central sampling command can be dispensed with and the switching synchronicity is improved, switching times are shortened and dynamic switching losses are reduced.
Complete Metadata
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| description | A method for dynamically balancing the loads in a circuit ( 1, 4 ) of semiconductor power switches arranged in series or in parallel is disclosed. Individual switching signals (i<SUB>G1</SUB>, i<SUB>G2</SUB>) for the semiconductor power switches (S<SUB>1 </SUB>. . . S<SUB>4</SUB>) are generated by determining a system-widely valid synchronous sampling time (ts<SUB>j</SUB>) independently for each semiconductor power switch (S<SUB>1 </SUB>. . . S<SUB>4</SUB>) due to a synchronous event (es) of the whole circuit ( 1, 4 ). Control loop offsets between actual values (a<SUB>i</SUB>) measured synchronously at the sampling time (ts<SUB>j</SUB>) and given desired values (a<SUB>s</SUB>) of an asynchronous state variable (a(t)) of the semiconductor power switches (S<SUB>1 </SUB>. . . S<SUB>4</SUB>) are reduced in the same or in following switching cycles. Alternatively, control loop offsets between actual time values (ta<SUB>i</SUB>) and desired time values (ta<SUB>s</SUB>) are minimized, wherein the actual time values (ta<SUB>i</SUB>) are measured upon exceeding a globally provided threshold value (epsilon<SUB>a</SUB>) of an asynchronous state variable (a(t)) of the semiconductor power switches (S<SUB>1 </SUB>. . . S<SUB>4</SUB>). Embodiments relate to: Offsetting the sampling time (ts<SUB>j</SUB>) in time by a globally provided time interval (Deltat 0 ), providing desired values locally or globally, e.g. by averaging of actual values (a<SUB>i</SUB>, ta<SUB>i</SUB>), additional balancing of the gradients of asynchronous time variables (a(t)). A central sampling command can be dispensed with and the switching synchronicity is improved, switching times are shortened and dynamic switching losses are reduced. |
| distribution |
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| title | Patent AT-E400924-T1: [Translated] METHOD FOR DYNAMIC SYMMETIZATION OF SERIES AND PARALLEL-CONNECTED POWER SEMICONDUCTOR SWITCHES |
